A Hardware Architecture for Gigabit Multicasting

The ultra-high data rate of modern communication media has challenged network designers to migrate communication protocol functions, traditionally implemented in software, to hardware. At the same time, new quality of service requirements from the higher-level network applications have complicated the functions of communication protocols. QuickRing is a high-speed slotted-ring network that consists of a single ring or multiple rings interconnected by bridges. The QuickRing multicast protocol provides an aggregate totally ordered delivery throughput of 1.3 Gbit/s and a latency of 5 s under low load. The Gbit/s transmission rate, and the short processing time of a few tens of nano-seconds for each arriving symbol, mandates hardware implementation of the protocol. We present a hardware architecture for the protocol chip, evaluate the complexity and feasibility of the design, and discuss various design trade-off issues. To our knowledge, this is the first attempt to support totally ordered multicasting in hardware.